NAND Flash memory circuits are being used to form memory system where the advantages of access speed are important. In many applications Flash memory systems are replacing mechanical disk drives with and exhibit a substantial decrease in read latency as well as a higher data throughput. Some memory system architectures employ a RAID (originally Reliable Array of Independent Disks) configuration to provide redundancy. Such Flash RAID memories may also be operated so as to minimize the deleterious performance effects associated with certain characteristics of NAND Flash circuits.
Generally, a NAND Flash circuit is organized as a plurality of blocks (e.g, 1024) of memory that are addressable as having a plurality of pages. A characteristic of this memory type is that the pages of a block must be “erased” before they can be re-written with new or modified data The minimum number of pages that can be erased is equal to an integral block in size. There may be, for example, 256 pages in a block. The number of bytes in a page has increased overtime as the technology has evolved, and has increased, for example, from 2 kB in early memories to 32 kB or 64 kB at the present time. Accessing a page for a read operation takes a period of time, perhaps 50 μs. Once accessed, the data of the opened page may be read in a short period of time, perhaps 3 μs.
The user of a memory system usually does not optimize the structure of data to be stored with respect to the specific architecture of the memory system. Rather, the user has selected page sizes and other data attributes so as to improve the efficiency of the data or signal processing performed in the user computer. Hence, a memory system often receives a heterogeneous mixture of data types and may receive data in a variety of page sizes. Page sizes of 512 bytes (typical of programs written for disk memory systems), 1 kB, 2 kB and 4 kB are often encountered. The page size used may be limited by the data transport protocol or other factors.
Further, the data of a received user page may be divided into chunks and stored in the memory circuits of a RAID group. One example is to take a received 4 kB page and divide it into 1 kB chunks, and to store the chunks and a parity chunk for the stored chunks in, for example, 5 separate memory circuits of a RAID group. Since this operation may result in portions of a plurality of user pages being stored in a Flash memory page, a user read request may be inefficient as only a portion of the Flash memory page, once opened, may contain the data that has been requested by the user.
A similar situation may occur when the process of reclaiming out-of-date pages is performed. This process is termed “garbage collection” and results in the moving of remaining valid data from the pages of a block of Flash memory to another block of memory or memory device prior to erasing the block. Since the user may have been addressing data in 4 kB page sizes, while the data was being stored in 64 kB sizes, only some of the portions of the data stored in the Flash pages may be invalid (e.g., data that has been modified and moved to another page of memory). The valid data needs to be manipulated so as to compress the valid data into a smaller number of pages to be moved so as to result in a completely invalid source block that can be erased. This process creates whole blocks of “erased” or “unprogrammed” memory that may again be used to store data.
The mismatch between user page sizes and Flash memory page sizes may lead to a fragmentation of the data such that access to the individual pages may be inefficient in terms of the amount of data read per Flash page access. The garbage collection (GC) process may also be considered as a user of the memory system as it performs reads and writes of data. In this circumstance the user is an internal user performing system overhead functions, including wear leveling.